Advanced Digital Power Processor (IXC2)


Features Include

  • Sixteen event processing channels with window control and two 100MHz programmable timing engines supporting eight driver outputs
  • Four event-driven timing engines
  • Four PWM channels (10ns resolution, 625ps fractional)
  • Peak-to-peak current mode control
  • phase shift control
  • Up to four interleaved timers with real-time programmable phase shift (any phase shift) with 10ns resolution
  • Simultaneous adjustable real-time update of frequency/duty
  • Rich power control-centric analog periphery
  • Four programmable dV/dt sensors (for soft switching timing)
  • Sixteen-channel 10-bit, 1.4MS/s ADC
  • Two four-channel 10-bit, 1.4MS/s ADC
  • 31 10ns fast comparators
  • 23 10-bit analog DACs for internal comparator threshold setting

Sample Applications

  • High efficiency Switch Mode Power Supplies (SMPS)
  • AC Battery inverters (uni-directional and bi-directional)
  • Single-panel and dual-panel micro-inverters
  • EV power converters / on-board chargers

Microcontroller for managing real-time power converters

 

The Solantro SA4041 (IXC2) Micro-Inverter Controller consists of mixed signal integrated circuits with analog sensing functions and digital processing. Each SA4041 (IXC2) IC contains a micro-processor based on a 32-bit RISC core, a set of peripherals for timing control, inter-IC communications, data memory, and general purpose digital inputs and outputs (GPIO).

The SA4041 (IXC2) provides the timing information for the power MOSFET drive signal processing and performs functions required for a power conversion circuit. The control of the conversion is based on the sampling of analog signals from the power train by the analog sensing block. These signals are then band-limited with anti-aliasing filters and digitized with high resolution analog-to-digital converters. Together with signals acquired from the current sensing block, they form an input to the real time control (RTC). The output of the RTC is a set of signals that control the power train through the driver timing control block. A communications port to the 32-bit micro- controller is available through the UART interfaces. The interface options for data link between ICs include one I2C and one SPI interface.

The control of the MOSFETs is based on sampling of the scaled down analog signals from the power train by the SA4041 (IXC2) voltage sensing block. The scaled down signals are band-limited with anti-aliasing filters and digitized with high resolution analog to digital converters. Together with signals from the current sensing block, they form an input to the SA4041 (IXC2) control algorithm. The output of the algorithm is a set of signals that control the power train through the driver timing control block.

The SA4041 (IXC2) architecture consists of a three-bus structure. This structure provides increased flexibility in the usage of the functional blocks, a fast interaction between them, and a powerful debugging mechanism where all of the important signals can be probed to verify the functionality of the device or system during the debugging or testing phase.  

 

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Ottawa ON, K2E7Y1

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